The present invention relates in general to integrated circuit chips, and in particular, to chips designed for multi-chip systems, especially to aspects of packaging, layout and inter-chip communication.
Operating speeds of integrated circuits, e.g., xe2x80x9cIC chipsxe2x80x9d, are ever increasing. Furthermore, according to another trend, chips with extremely dense circuitry and input and output (xe2x80x9ci/oxe2x80x9d) traffic are being implemented on one chip and are being packaged as high-speed, multi-chip systems. High-speed processor chips are an example of this trend. These developments lead to a need to transmit signals between chips at high speeds.
There is a potential to improve communication and operating speeds by locating chips, and especially their external interface connection points, close to one another. However, the layout of these very dense chips, including their external connections, is a very complicated matter, making it difficult to design features in their layout which permit such chips to be packaged close to one another.
As a result, there is a need in the art for improvements in chip and package layout, as well as inter-chip communication methods, in order to address the foregoing needs.
The present invention addresses the forgoing needs in a multi-chip apparatus, i.e., a module having a number of integrated circuit chips. The chips are disposed on a carrier and are electrically coupled in a communications ring. The communications ring has module portions disposed on the module and chip portions disposed on the respective chips.
In one aspect, the portions of the ring disposed on the carrier (the xe2x80x9ccarrier ring portionsxe2x80x9d) are substantially straight, whereas at least one of the portions of the ring disposed on the chips (the xe2x80x9cchip ring portionsxe2x80x9d) has a turn to enable the closure of the ring. This is particularly beneficial, because fabrication techniques generally permit the conductors on a chip to be spaced relatively more close together than conductors on a carrier.
In another aspect, the chips include respective regeneration circuitry interposed in the respective chip portions of the communications ring, for regenerating communications signals traversing the respective chips on the respective chip portions of the ring.
According to one form of the invention, the apparatus has, disposed on a carrier, a plurality of N integrated circuit chips, and N bus sets (the xe2x80x9ccarrier bus setsxe2x80x9d). The N chips have respective first and second i/o sets, one of the i/o sets of a first one of the chips is electrically coupled, by a first one of the carrier bus sets, to a corresponding one of the i/o sets of a second one of the chips. One of the i/o sets of the second chip is electrically coupled, by a second one of the carrier bus sets, to a corresponding one of the i/o sets of a third one of the chips, and so on through chip N. In addition, one of the i/o sets of the Nth chip is electrically coupled, by an Nth one of the carrier bus sets, to a corresponding one of the i/o sets of the first chip, thereby closing the ring. Thus, that the chips are electrically coupled for communicating in a ring. Furthermore, according to this form the corresponding i/o sets of the first and second chip are in substantial alignment, the corresponding i/o sets of the second and third chip are in substantial alignment, the corresponding i/o sets of the third and fourth chips are in substantial alignment, and the corresponding i/o sets of the fourth and first chip are in substantial alignment.
This alignment of the corresponding i/o sets advantageously facilitates the previously mentioned, substantially straight module portions of the ring.
Furthermore, according to another aspect, the first i/o sets are associated with a first edge of their respective chips and the second i/o sets are associated with a second edge of their respective chips.
In one particular aspect, where N is four, the first edges are adjacent to the respective second edges. With respect to a plane of the chip carrier, the second chip is rotated 90 degrees relative to the first chip, the third chip is rotated 90 degrees relative to the second chip, and the fourth chip is rotated 90 degrees relative to the third chip. According to this orientation of the chips, the corresponding i/o sets of the first and second chip are in substantial alignment, the corresponding i/o sets of the second and third chip are in substantial alignment, the corresponding i/o sets of the third and fourth chips are in substantial alignment, and the corresponding i/o sets of the fourth and first chip are in substantial alignment, so that the corresponding i/o sets are interconnected by substantially straight carrier buses disposed on the carrier.
In an aspect of the above, the chips have chip buses disposed on the respective chips. The interconnected carrier buses and chip buses provide a communication ring, the ring having the carrier buses disposed on the carrier for signals from chip-to-chip, and the chip buses disposed on the respectine chips for signals traversing the chips.
It is an advantage of the present invention that it establishes clean timing boundaries between chips based on the relative location of one with respect to another and, in the four chip embodiment, further allocates the longer physical distance case to two cycles so as to ensure that chip-to-chip,timing does not become the cycle time limiting factor.
The foregoing has outlined rather broadly features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.